Digital phase locking system

Abstract

PURPOSE:To quicken the acquisition of synchronism at out of synchronism and suppress effectively jitter after the acquisition of synchronism, by generating a 2-phase clock pulse from an output of a clock pulse generator, switching the 2- phase clock at the changing point of an input signal so as to compare the phases of an input and an output signal. CONSTITUTION:Two-phase clock pulses phi0, phi1 are outputted from the clock pulse generator 1 and applied to a selector 3. Further, the phases of the input and the output signal are compared at a phase comparator 11 and the locking of the phase is taken at the 1st digital locked circuit with the control whether or not one pulse in a pulse train switched at the selector 3 is inhibited. Moreover, the result of phase comparison at the comparator 11 is inputted to an up-down counter 12, and when the counter 12 oveflows or underflows, the phase is locked at the 2nd digital phase locked circuit depending whether one pulse in the pulse train after the switching to the 2nd pulse phi1 is inhibited. Then, the 2nd locked circuit is used normally and when the counter 12 gives an output, the 1st locked circuit is used.

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