Integrated memory matrix with nonvolatile and reprogrammable storage cell

  • Inventors: BURUKUHARUTO GIIBERU
  • Assignees: Itt
  • Publication Date: March 09, 1984
  • Publication Number: JP-S5942695-A

Abstract

The invention discloses an integrated memory matrix comprising nonvolatile reprogrammable storage (memory) cells arranged in rows and columns, as well as a classifying circuit integrated as well in the semiconductor body of the memory matrix, containing a nonprogrammable reference storage cell (Mr) of the same construction as that of the storage cells, and which is manufactured simultaneously as a comparison standard, with the storage cells. With the aid of a first voltage divider (Q1) integrated as well, whose output voltage is adjustable in steps, and whose output current is fed into the source-drain line of the reference storage cell (Mr) and/or of a second voltage divider (Q2) adjustable in steps and integrated as well, whose output voltage is applied to the control gate of the storage transistor (Ts) of the reference storage cell (Mr), it is possible to simulate a threshold voltage which is compared with the threshold voltages of the storage cells (M11 . . . Mmn) of the memory matrix (S) either individually or in groups with the aid of a comparator circuit (Ad) for obtaining a classifying criterion.

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    Publication numberPublication dateAssigneeTitle
    JP-S62164300-AJuly 20, 1987Texas Instruments IncElectrically erasable/programmable semiconductor memory cell